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LTC3725 Single-Switch Forward Controller and Gate Driver
FEATURES

DESCRIPTIO

High Speed Gate Driver for Forward Converter On-Chip Rectifier and Self-Starting Architecture Eliminates Need for Separate Gate Drive Bias Supply Wide Input Voltage Supply Range: 9V and Up Linear Regulator Controller for Fast Start-Up Precision UVLO with Adjustable Hysteresis Overcurrent Protection Volt-Second Limit Prevents Transformer Core Saturation Voltage Feedforward for Fast Transient Response Available in 10-Lead MSOP Package
The LTC(R)3725 is a controller for a single-switch forward converter and includes an on-chip gate driver. For secondary-side control, combine the LTC3725 with the LTC3706 PolyPhase(R) secondary-side synchronous forward controller to create a complete forward converter using a minimum of discrete parts. A proprietary scheme is used to multiplex gate drive signals across the isolation barrier through a tiny pulse transformer. The on-chip rectifier and the same pulse transformer provide gate drive bias power. Alternatively, the LTC3725 can be used as a standalone voltage mode controller in a primary-side control architecture with optoisolator feedback. Voltage feedforward provides excellent line regulation and transient response.
, LTC and LT are registered trademarks of Linear Technology Corporation. PolyPhase is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patent Pending
APPLICATIO S

Isolated 48V Telecommunication Systems Internet Servers and Routers Distributed Power Step-Down Converters Automotive and Heavy Equipment
TYPICAL APPLICATIO
VIN 36V TO 72V
+
36V-72V to 3.3V/30A Isolated Single-Switch Forward Converter
T1
* *
1F 100V x2 Si7450DP 0.030 1W 2.2nF 200V
*
HAT2165 x2 0.0012 1W HAT2165 x2
VIN-
FDC2512
100k GATE IS FB/IN+ 0.1F T2 5.1k 1F PT+ FG SW I S- IS +
NDRV 365k 1F 15k VCC UVLO
SG VIN NDRV VCC MODE
*
*
LTC3706 PT- GND PGND RUN/SS SLP REGSD FS/SYNC PHASE FB
LTC3725
FS/IN- SSFLT VSLMT PGND GND 33nF
162k 33nF 100k 470pF
L1: PULSE PA1294.910 T1: PULSE PA0815 T2: PULSE PA0297
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L1 0.85H VOUT+ 3.3V 30A 100F 6.3V x2 B0540W
U
U
+
1.2 1/4W 10F
220F 6.3V
VOUT- FCX491A 2.2F 2.74k
ITH 604 3.3k 47nF
3725 TA01
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1
LTC3725
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW UVLO SSFLT NDRV FB/IN+ FS/IN- 1 2 3 4 5 10 9 8 7 6 IS VSLMT VCC GATE PGND
Power Supply (VCC) ...................................- 0.3V to 15V External NMOS Drive (NDRV) ....................- 0.3V to 20V NDRV to VCC ........................................................... - 0.3V to 5V Soft-Start Fault, Feedback, Frequency Set, Transformer Inputs (SSFLT, FB/IN+, FS/IN-) ..................- 0.3V to 15V All Other Pins (VSLMT, IS, UVLO) .................- 0.3V to 5V Peak Output Current <1s (GATE) ............................. 2A Operating Ambient Temperature Range .. - 40C to 85C Operating Junction Temperature (Note 2) ............ 125C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
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MSE PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125C, JA = 45C/W, JC = 10C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
ORDER PART NUMBER LTC3725EMSE LTC3725IMSE
MSE PART MARKING LTBSV LTBSW
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges.
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 12V, GND = PGND = 0V, TA = 25C, unless otherwise noted.
SYMBOL VCCOP VCCLR INDRV tr(VCC) INDRVTO ICC ICCM VCCSR ICCSR PARAMETER Operating Voltage Range Output Voltage Current into NDRV Pin Rise Time of VCC Linear Regulator Time Out Current Threshold Supply Current Maximum Supply Current Maximum Supply Voltage Minimum Current into NDRV/VCC Linear Regulator in Operation Linear Regulator in Operation Linear Regulator Charging (0.5V to 7.5V) Primary-Side Operation VUVLO = 1.5V, Linear Regulator in Operation (Note 3) VUVLO = 1.5V, Trickle Charger in Operation, VCC = 13.2V (Note 3) Trickle Charger Shunt Regulator Trickle Charger Shunt Regulator, VCC = 15V (Note 3) VCC Rising VCC Falling VCC Rising (Linear Regulator) VCC Rising (Trickle Charger) VCC Falling

ELECTRICAL CHARACTERISTICS
CONDITIONS
MIN 7 0.1
TYP 12 8
MAX 15 1
UNITS V V mA s mA
VCC Supply, Linear Regulator and Trickle Charger Shunt Regulator
45 0.27 1.4 1.7 14.25 10 2.1 2.5 15
Internal Undervoltage VCCUV Internal Undervoltage Threshold 5.3 4.7 7.2 13.1 6.8 7.4 13.4 7.0 7.7 14 7.2 V V V V V
Gate Drive Undervoltage VGDUV Gate Drive Undervoltage Threshold
2
U
mA mA V mA
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WW
W
LTC3725
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 12V, GND = PGND = 0V, TA = 25C, unless otherwise noted.
SYMBOL VUVLOR VUVLOF IHUVLO VUVLOOP ROS VOH IPU tr tf Rectifier IRECT Oscillator fOSC(P) Oscillator Frequency Primary-Side Control, RFS(P) = 100k Primary-Side Control, RFS(P) = 25k Primary-Side Control, RFS(P) = 300k Primary-Side Control 25k < RFSET < 300k Secondary-Side Control (During Start-Up), RFS(S) = 100k Primary-Side Control, VSSFLT = 2V Secondary-Side Control, VUVLO = 1.3V, VSSFLT = 2V Secondary-Side Control, VUVLO = 3.75V, VSSFLT = 2V VCC = 8V Timing Out After Fault, VSSFLT = 2V 200 700 70 15 300 kHz kHz kHz % kHz Maximum Rectifier DC Output Current 25 mA PARAMETER Undervoltage Lockout Threshold Rising Undervoltage Lockout Threshold Falling Hysteresis Current Voltage Feedforward Operating Range Output Pull-Down Resistance High Output Voltage Peak Pull-Up Current Output Rise Time Output Fall Time 10% to 90%, COUT = 4.7nF 10% to 90%, COUT = 4.7nF CONDITIONS Rising Falling VUVLO = 1V Primary-Side Control IOUT = 100mA IOUT = -100mA

ELECTRICAL CHARACTERISTICS
MIN 1.220 1.205 4.2 VUVLOF(MIN)
TYP 1.242 1.226 4.9
MAX 1.280 1.265 5.6 3.75
UNITS V V A V V A ns ns
Undervoltage Lockout (UVLO)
Gate Driver (GATE) 1.9 11 1.7 40 70
fRFS(P) fOSC(S)
Oscillator Resistor Set Accuracy Oscillator Frequency
Soft-Start/Fault (SSFLT) ISS(C) Soft-Start Charge Current -5.2 -4 -1.6 3.9 6.7 1 300 1.26 0.25 Primary-Side Control IFB = 0V Primary-Side Control VFB = 2.5V Primary-Side Control VFB = 0V 3.3 0.5 1.6 A A A V V A mV V mA V mA mA
VLRTO VFLTH ISS(D) VIS(MAX) VVSL(MAX) IVSLMT(MAX) VOPTO IOPTO
Linear Regulator Time Out-Threshold Fault Output High Soft-Start Discharge Current Overcurrent Threshold Volt-Second Limit Threshold Maximum Volt-Second Limit Resistor Current Open Circuit Optoisolator Voltage Optoisolator Bias Current
Current Sense Input (IS) Volt Second Limit (VSLMT)
Optoisolator Bias Current
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Operating junction temperature TJ (in C) is calculated from the ambient temperature TA and the average power dissipation PD (in watts)
by the formula: TJ = TA + JA * PD. Refer to the Applications Information section for details. Note 3: ICC is the sum of current into NDRV and VCC.
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LTC3725 TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs VCC
2.0 TRICKLE CHARGER 1.240
UVLO THRESHOLD (V)
1.5
CURRENT (mA)
LINEAR REGULATOR 1.0
1.235
IHUVLO (A)
0.5
0
0
5 VCC (V)
10
Oscillator Frequency fOSC vs RFSET
800 700 600
OSCILLATOR FREQUENCY fOSC(P) (kHz)
fOSC (kHz)
400 300 200 100 PRIMARY-SIDE CONTROL 0 0 100 200 RFSET (k) 300 400
3725 G04
200 199 198
PRIMARY-SIDE CONTROL RFS(P) = 100k
ICC (mA)
500
SECONDARY-SIDE CONTROL
Shunt Regulator Current vs Temperature
25 24 23 12 22 14 13
ICCSR (mA)
VFB/IN+ (V)
VGDUV (V)
21 20 19 18
17 16 15 20 40 60 -60 -40 -20 0 TEMPERATURE (C) 80 100 7
4
UW
15
3725 G01
3725 G07
UVLO Voltage Threshold vs Temperature
1.245 5.05
UVLO Hysteresis Current vs Temperature
VUVLOR
5.00
4.95
1.230
4.90
1.225 VUVLOF 1.220 20 40 60 -60 -40 -20 0 TEMPERATURE (C) 80 100
4.85
4.80 20 40 60 -60 -40 -20 0 TEMPERATURE (C)
80
100
3725 G02
3725 G03
Oscillator Frequency vs Temperature
203 202 201 18 15 12 9 6 3
Shunt Regulator Current ICC vs VCC
197 20 40 60 -60 -40 -20 0 TEMPERATURE (C)
80
100
0 14.00
14.25
14.50 VCC (V)
14.75
15.00
3725 G06
3725 G05
VGDUV vs Temperature
3.5 VCC RISING (TRICKLE CHARGER) 3.0 2.5 2.0 1.5 1.0 0.5 VCC FALLING (BOTH) 6 20 40 60 -60 -40 -20 0 TEMPERATURE (C) 80 100 0
Optoisolator Bias VFB/IN+ vs IFB/IN+
11 10 9 8 VCC RISING (LINEAR REGULATOR)
0
0.5
1.0 -IFB/IN+ (mA)
1.5
2.0
3725 G09
3725 G08
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LTC3725 TYPICAL PERFOR A CE CHARACTERISTICS
Gate Drive Pull-Down Resistance vs Temperature
2.50 2.0
GATE DRIVE RESISTANCE ROS ()
2.25 1.8
2.00
IPU (A)
1.75
1.50 20 40 60 -60 -40 -20 0 TEMPERATURE (C)
Linear Regulator Start-Up
VIN
5V/DIV NDRV
VCC 25s/DIV
3725 G12
UW
Gate Drive Peak Pull-Up Current vs Temperature
1.9
1.7
1.6
80
100
1.5 20 40 60 -60 -40 -20 0 TEMPERATURE (C)
80
100
3725 G10
3725 G11
Gate Drive Encoding
GATE FB/IN 10V/DIV
10V/DIV
Fault Operation
GATE
SSFLT
FS/IN-
2V/DIV
3705 G13
1s/DIV
40ms/DIV
3725 G14
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LTC3725
PI FU CTIO S
UVLO (Pin 1): Undervoltage Lockout. Connect to a resistive voltage divider to monitor input voltage VIN. Enables converter operation for VUVLO > 1.242V. Hysteresis is a fixed 16mV hysteresis voltage with a 4.9A hysteresis current that combines with the Thevenin resistance of the divider to set the total UVLO hysteresis voltage. This input also senses VIN for voltage feedforward. Finally, this pin can be used for external run/stop control. SSFLT (Pin 2): Combination Soft-Start and Fault Indicator. A capacitor to GND sets the duty cycle ramp-up rate during start-up. To indicate a fault, the SSFLT pin is momentarily pulled up to within 1.3V of VCC. NDRV (Pin 3): Drive for the External NMOS Linear Regulator. Connect to the gate of the NMOS and connect a pull up resistor to the input voltage (VIN). Optionally, to create a trickle charger omit the NMOS device and connect NDRV to VCC. FB/IN+ (Pin 4): This pin has several functions. One winding of a pulse transformer is connected to the FB/IN+ and FS/IN- pins. The other pulse transformer winding is connected to the LTC3706. The LTC3725 automatically detects when the LTC3706 applies a pulse-encoded signal to the FB/IN+ and FS/IN- pins and decodes duty cycle information for control of the primary-side gate drive (see Operation below). In secondary-side control, primaryside gate drive bias power is also extracted from the FB/IN+ and FS/IN- pins using an on-chip full-wave rectifier. For primary-side control connect this pin to an optoisolator for feedback control of converter output voltage using an internal optoisolator biasing network. FS/IN- (Pin 5): This pin has several functions. Place a resistor from this pin to GND to set the oscillator frequency. For secondary-side control with the LTC3706, connect one winding of the pulse transformer for operation as described for the FB/IN+ pin above. PGND (Pin 6): Supply Return for the Bottom Gate Driver and the On-Chip Bridge Rectifier. GATE (Pin 7): Gate Drive. Connect to the gate of the external MOSFET. VCC (Pin 8): Main VCC Power for All Driver and Control Circuitry. VSLMT (Pin 9): Volt-Second Limit. Form an R-C integrator by connecting a resistor from VIN to VSLMT and a capacitor from VSLMT to ground. The gate drive is turned off when the voltage on the VSLMT pin exceeds 1.26V. IS (Pin 10): Input to the Overcurrent Comparator. Connect to the positive terminal of a current-sense resistor in series with the source of the ground-referenced bottom MOSFET. GND (Pin 11): Signal Ground.
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LTC3725
BLOCK DIAGRA
+
NDRV 3 0.6V
- + -
7.4V/7V LINEAR REGULATOR 13.4V/7V TRICKLE TRICKLE CHARGE CHARGER
INDRV
0.27mA
-V
SSFLT 2
+
OC
1.242V 1.226V UVLO 1 VFF 0.66
+ -
4.9A
UVVIN
GND 11 (PAD)
PWM RECEIVER IN+ IN -
PWM SECONDARY CONTROL 5V
SW DET
CONDITION
SW DET
DRIVE LOGIC
+ -
400mV PWM PRIMARY CONTROL
N/C 2V RAMP VP-P VP-P
FREQUENCY SET
OSCILLATOR CLOCK
0V
OPTO BIAS
3.3V FB/IN + 4
IOSC SECONDARY SIDE CONTROL VCC 8 VCC 7 GATE PGND 6 PGND
3725 BD
RECTIFIER
FS/IN - 5
-
PRIMARY SIDE CONTROL
+
-
+
W
8V SHUNT REGULATOR VCC 5V REGULATOR
- +
+
UVGD 14.25V
- +
UVINT
5.3V/4.7V LINE OFF TIME SOFT-START FAULT
-
10 IS
300mV
1.26V
9 VSLMT
SWITCH ON
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LTC3725
OPERATIO
Mode Setting The LTC3725 is a controller and gate driver designed for use in a single-switch forward converter. When used in conjunction with the LTC3706 PolyPhase secondaryside synchronous forward controller, it forms a complete forward converter with secondary-side regulation, galvanic isolation between input and output, and synchronous rectification. In this mode, upon start-up, the FB/ IN+ and FS/IN- pins are effectively shorted by one winding of the pulse transformer. The LTC3725 detects this short circuit to determine that it is in secondary-side control mode. Operation in this mode is confirmed when the LTC3706 begins switching the pulse transformer. Alternately, the LTC3725 can be used as a standalone primary-side controller. In this case, the FB/IN+ and FS/IN- pins operate independently. The FB/IN+ pin is connected to the collector of an optoisolator to provide feedback and the FS/IN- pin is connected to the frequency set resistor. Gate Drive Encoding In secondary-side control with the LTC3706, after a startup sequence, the LTC3706 transmits multiplexed PWM information through a pulse transformer to the FB/IN+ and FS/IN- inputs of the LTC3725. In the LTC3725, the PWM receiver extracts the duty cycle and uses it to control the gate driver. Figure 1 shows that the LTC3706 drives the pulse transformer in a complementary fashion, with a duty cycle of approximately 75%. At the appropriate time during the positive half cycle, the LTC3706 applies a short (150ns) zerovoltage pulse across the pulse transformer, indicating the
DUTY CYCLE = 15% 150ns 150ns +7V DUTY CYCLE = 0% 150ns
VPT1+ - VPT1-
-7V 1 CLK PER 1 CLK PER
3725 F01
Figure 1. Gate Drive Multiplexing Scheme
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end of the "on" time. Although this scheme allows the transmission of 0% to 75% duty cycle, it is necessary to establish a minimum controllable "on" time of approximately 100ns. This ensures that 0% duty cycle can be reliably distinguished from 75% duty cycle. On-Chip Rectifier Simultaneously with duty-cycle decoding, and through the same pulse transformer, the wave generated by the LTC3706 provides primary-side VCC gate drive bias power by way of the LTC3725's on-chip full-wave bridge rectifier. No auxiliary bias supply is necessary and forward converter design and circuitry are considerably simplified. External Series Pass Linear Regulator The LTC3725 features an external series pass linear regulator that eliminates the long start-up time associated with the conventional trickle charger. The drain of an external NMOS is connected to the input voltage and the source is connected to VCC. The gate of the NMOS is connected to NDRV. To power the gate, an external pull-up resistor is connected from the input voltage to NDRV. The NMOS must be a standard 3V threshold type (i.e. not logic level). An on-chip circuit manages the start up and operation of the linear regulator. It takes approximately 45s for the linear regulator to charge VCC to its target value of 8V (unless limited by a slower rise of VIN). The LTC3725 begins operating the gate drives when VCC reaches 7.4V. Often, the thermal rating of the NMOS prevents it from operating continuously, and the LTC3725 "times out" the linear regulator to prevent overheating. This is accomplished using the capacitor connected to the SSFLT pin as described subsequently. Trickle Charger Shunt Regulator Alternately, a trickle charger can be implemented by eliminating the external NMOS and connecting NDRV to VCC and using the pull-up resistor to charge VCC. To allow extra headroom for starting, the LTC3725 detects this mode and increases the threshold for starting the gate drives to 13.4V. An internal shunt regulator limits the voltage on the trickle charger to 15V.
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LTC3725
OPERATIO
Self-Starting Architecture The LTC3725 is combined with the LTC3706 to form a complete self-starting DC isolated power supply. When power is first applied, and when VCC for the LTC3725 is above the appropriate threshold, the LTC3725 begins open-loop operation using its own internal oscillator. Power is supplied to the secondary by switching the gate driver with a gradually increasing duty cycle as controlled by the rate of rise of the voltage on the SSFLT pin. A peak detector power supply for the LTC3706 allows it to begin operation even for small duty cycles. Once adequate voltage is available for the LTC3706, it provides duty cycle information and gate drive bias power using the pulse transformer as shown in Figure 1. The LTC3725 detects the appearance of this signal and transfers control of the gate drivers to the LTC3706. Simultaneously, the LTC3725 also enables the on-chip rectifier and turns off the linear regulator. Alternately, when the LTC3725 is used as a standalone primary-side controller, the gradually increasing duty cycle powers up a secondary-side reference and optoisolator and feedback is accomplished when the output of the optoisolator begins pulling down in the FB/IN+ pin. Soft-Start and Fault These two functions are implemented using the SSFLT pin. (This pin is also used for linear regulator timeout as described in the following section.) Initiating soft-start requires that: 1) the gate drive undervoltage (UVGD) goes low meaning that adequate voltage is available on the VCC pin (7.4V for the linear regulator or 13.4V for the trickle charger) and 2) the input undervoltage (UVVIN) goes low meaning that the voltage on the UVLO pin has reached the 1.242V rising threshold. During soft-start, the LTC3725 gradually charges the softstart capacitor to ramp up the converter duty cycle. Softstart is over when the voltage on the SSFLT pin reaches 2.8V. In normal operation, at some point before this, the LTC3725 makes a transition to controlling duty cycle using closedloop regulation of the converter output voltage.
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The SSFLT pin is also used to indicate a fault. The LTC3725 recognizes faults from four origins: 1) an overcurrent fault caused by the current sense voltage on the IS pin exceeding the 300mV overcurrent threshold, 2) an input undervoltage fault caused by the UVLO pin falling below the 1.226V falling threshold, 3) a gate drive undervoltage fault caused by the voltage on the VCC pin falling below the 7V threshold, or 4) loss of the gate drive encoding signal from the LTC3706. Upon sensing a fault, the LTC3725 immediately turns off the gate drive and indicates a fault by quickly pulling the voltage on the SSFLT pin to within 1.3V of the voltage on the VCC pin. After indicating the fault, the LTC3725 quickly ramps down the voltage on the SSFLT pin to approximately 2.8V. Then, to allow complete discharge of the secondary-side circuit, the LTC3725 slowly ramps down the voltage on the SSFLT pin to about 200mV. The LTC3725 then attempts a restart. Linear Regulator Timeout The thermal rating of the linear regulator's external NMOS often cannot allow it to indefinitely supply bias current to the primary-side gate drives. The LTC3725 has a linear regulator timeout mechanism that also uses the SSFLT capacitor. As described in the prior section, soft-start is over once the voltage on the SSFLT pin reaches 2.8V. However, the SSFLT capacitor continues to charge and the linear regulator is turned off when the voltage on the SSFLT pin reaches 3.9V. The "Applications Information" section describes linear regulator timeout in more detail. Volt-Second Limit The volt-second limit ensures that the power transformer core does not saturate for any combination of duty cycle and input voltage. The input of an R-C integrator is connected to VIN and its output is connected to the VSLMT pin. While the gate drive is "off," the LTC3725 grounds the VSLMT pin. When the gate drive is turned "on" the VSLMT pin is released and the capacitor is allowed to charge in proportion to VIN. If the capacitor voltage on the VSLMT pin
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LTC3725
OPERATIO
exceeds 1.26V the gate drive is immediately turned "off." Note that this is not considered a fault condition and the LTC3725 can run indefinitely with the switch duty cycle being determined by the volt-second limit circuit. The duty cycle is always limited to 75% to ensure that the power transformer flux always has time to reset before the start of the next cycle. In an alternate application, the volt-second limit can be used for open-loop regulation of the output against changes in VIN. Current Limit Current limit for the LTC3725 is principally a safety feature to protect the converter and is not part of a control function. The current that flows in series through the transformer primary and the switch is sensed by a resistor connected between the source of the switch and GND. If the voltage across this resistor exceeds 300mV, the LTC3725 initiates a fault. Voltage Feedforward The LTC3725 uses voltage feedforward to properly modulate the duty cycle as a function of the input voltage. For secondary-side control with the LTC3706, voltage feedforward is used during start-up only. The duty cycle during start up is determined by comparison of the voltage on the SSFLT pin to a 75% duty cycle triangle wave with
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an amplitude of 2V. To implement voltage feedforward, the charging current for the soft-start capacitor is reduced in proportion to the input voltage. As a result, the initial rate of rise of the converter output voltage is held approximately constant regardless of the input voltage. At some point during start-up, the LTC3706 begins to switch the pulse transformer and take over the soft-start. For operation with standalone primary-side control and optoisolator feedback, voltage feedforward is used during both start-up and normal operation. The duty cycle is determined by using a 75% duty cycle triangle wave with an amplitude equal to 66% of the voltage on the UVLO pin which is, in turn, proportional to VIN. The charging current for the soft-start capacitor is a constant 5.2A. During soft-start, the duty cycle is determined by comparing the voltage on the SSFLT pin to the triangle wave. Soft-start is concluded when the voltage on the SSFLT pin exceeds the voltage on the FB/IN+ pin. After the conclusion of softstart, the duty cycle is determined by comparison of the voltage on the FB/IN+ pin to the triangle wave. Optoisolator Bias When the LTC3725 is used in standalone primary-side mode, feedback is provided by an optoisolator connected to the FB/IN+ pin. The LTC3725 has a built optoisolator bias circuit which eliminates the need for external components.
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LTC3725
APPLICATIO S I FOR ATIO
UVLO The UVLO pin is connected to a resistive voltage divider connected to VIN as shown in Figure 2. The voltage threshold on the UVLO pin for VIN rising is 1.242V. To introduce hysteresis, the LTC3725 draws 4.9A from the UVLO pin when VIN is rising. The hysteresis is therefore user adjustable and depends on the value of R1. The UVLO threshold for VIN rising is: R1+ R2 + R1(4.9A) R2 The LTC3725 also has 16mV of voltage hysteresis on the UVLO pin so that the UVLO threshold for VIN falling is: VIN(UVLO, RISING) = (1.242V) VIN(UVLO, FALLING) = (1.226V) R1+ R2 R2
To implement external Run/Stop control, connect a small NMOS to the UVLO pin as shown in Figure 2. Turning the NMOS on grounds the UVLO pin and prevents the LTC3725 from running.
VIN
R1 UVLO LTC3725 RUN/STOP CONTROL (OPTIONAL)
3725 F02
R2
GND
Figure 2. Resistive Voltage Divider for UVLO and Optional Run/Stop Control
Linear Regulator The linear regulator eliminates the long start-up times associated with a conventional trickle charger by using an external NMOS to quickly charge the capacitor connected to the VCC pin.
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Note that a trickle charger usually requires a large capacitor to provide holdup for the VCC pin while the converter attempts to start. The linear regulator in the LTC3725 can both charge the capacitor connected to the VCC pin and provide primary-side gate-drive bias current. Therefore, with the linear regulator, the capacitor need only be large enough to cope with the ripple current from driving the gate of the primary FET and holdup need not be considered. The external NMOS for the linear regulator should be a standard 3V threshold type (i.e. not a logic level threshold). The rate of charge of VCC from 0V to 8V is controlled by the LTC3725 to be approximately 45s regardless of the size of the capacitor connected to the VCC pin. The charging current for this capacitor is approximately:
IC = 8V C 45s
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The safe operating area (SOA) for the external NMOS should be chosen so that capacitor charging does not damage the NMOS. Excessive values of capacitor are unnecessary and should be avoided. Start-Up Considerations When used in a self-starting converter with the LTC3706, the LTC3725 initially begins the soft-start of the converter in an open-loop fashion. After bias is obtained on the secondary side, the LTC3706 assumes control and completes the soft-start interval. In order to ensure that control is properly transferred from the LTC3725 (primary-side) to the LTC3706 (secondary-side), it is necessary to limit the rate of rise on the primary-side soft-start ramp so that the LTC3706 has adequate time to wake up and assume control before the output voltage gets too high. This condition is satisfied for many applications if the following relationship is maintained: CSS,SEC CSS_PRI
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LTC3725
APPLICATIO S I FOR ATIO U
LTC3725, the linear regulator times out resulting in a gate drive undervoltage fault, or 2) the primary-side overcurrent circuit is tripped because of current buildup in the output inductor. In either case, the LTC3725 initiates a shutdown followed by a soft-start retry. Linear Regulator Timeout After start-up, the LTC3725 times out the linear regulator to prevent overheating of the external NMOS. The timeout interval is set by further charging the soft-start capacitor CSSFLT from the end-of-soft-start voltage of approximately 2.8V to the timeout threshold of 3.9V. Linear regulator timeout behaves differently depending on mode. In primary-side standalone mode, the LTC3725 generally requires that an auxiliary gate drive bias supply take over from the linear regulator. (See the subsequent section for more detail on the auxiliary supply.) During linear regulator timeout, the rate of rise of the soft-start capacitor voltage depends on the current into the NDRV pin as controlled by the pull-up resistor RPULLUP, the value of VIN and the value of VNDRV.
However, care should be taken to ensure that soft-start transfer from primary-side to secondary-side is completed well before the output voltage reaches its target value. A good design goal is to have the transfer completed when the output voltage is less than one-half of its target value. Note that the fastest output voltage rise time during primary-side soft-start mode occurs with minimum load current. The open-loop start-up frequency on the LTC3725 is set by placing a resistor RFS(S) from the FS/IN- pin to GND. Although the exact start-up frequency on the primary side is not critical, it is generally a good practice to set it approximately equal to the operating frequency on the secondary side. In this mode the start-up frequency of the LTC3725 is approximately:
f PRI = 34 * 109 RFS(S) + 10, 000
In the event that the LTC3706 fails to start up properly and assume control of switching, there are several fail-safe mechanisms to help avoid overvoltage conditions. First, the LTC3725 implements a volt-second clamp that may be used to keep the primary-side duty cycle at a level that does not produce an excessive output voltage. Second, the timeout of the linear regulator (described in the following section) means that, unless the LTC3706 starts and supports the LTC3725 gate drive through the pulse transformer and on-chip rectifier, the LTC3725 eventually suffers a gate drive undervoltage fault. Finally, the LTC3706 has an independent overvoltage detection circuit that crowbars the output of the DC/DC converter using the synchronous secondary-side MOSFET switch. In the event that a short-circuit is applied to the output of the converter prior to start-up, the LTC3706 generally does not receive enough bias voltage to operate. In this case, the LTC3725 detects a FAULT for one of two reasons: 1) since the LTC3706 never sends pulse encoding to the
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VIN - VNDRV RPULLUP The value of VNDRV is VCC = 8V plus the value of the gateto-source voltage (VNDRV - VCC) of the external NMOS in the linear regulator. The gate-to-source voltage depends on the actual device but is approximately the threshold voltage of the external NMOS. INDRV =
For INDRV > 0.27mA, the capacitor on the SSFLT pin is charged in proportion to (INDRV - 0.27mA) until the linear regulator times out. Thus, since VNDRV is very nearly constant, the timeout interval for the linear regulator is inversely proportional to the input voltage and a higher input voltage produces a shorter timeout.
tTIMEOUT =
66C SSFLT (3.9V - 2.8V) VIN - VNDRV - 0.27mA R PULLUP
3725f
LTC3725
APPLICATIO S I FOR ATIO
Since the power dissipation of the linear regulator is proportional to the input voltage, this strategy of making the timeout inversely proportional to the input voltage produces an approximately constant temperature excursion for the external NMOS of the linear regulator regardless of the input voltage. In situations for which the continuous operation of the linear regulator does not exceed the thermal limitations of the external NMOS (i.e. converters with low VIN or with minimal gate drive bias requirements), the auxiliary supply can be omitted and the linear regulator allowed to operate continuously. If INDRV is less than 0.27mA the linear regulator never times out and the voltage on the SSFLT pin stays at approximately 2.8V after start-up is completed. To accomplish this set:
VIN(MAX) - VNDRV 0.27mA where VIN(MAX) is the maximum expected continuous input voltage. Note that once the linear regulator is turned off it locks out. Therefore when using this strategy, care should be taken to ensure that a transient higher than VIN(MAX) does not persist longer than t TIMEOUT. RPULLUP >
In secondary-side operation with the LTC3706, there is never any need for continuous operation of the linear regulator since gate drive bias power is provided by the LTC3706 through the pulse transformer and on-chip rectifier. The LTC3725 shuts down the linear regulator once the LTC3706 begins switching the pulse transformer. If the LTC3706 fails to start, the LTC3725 quickly times out the linear regulator once the voltage on the SSFLT pin reaches 2.8V.
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Fault Lockout The LTC3725 indicates a fault by pulling the SSFLT pin to within 1V of VCC. The LTC3725 subsequently attempts a restart. Optionally, the user can prevent restart and "lock out" the converter by clamping the voltage on the SSFLT pin with a 4.3V zener diode. Once the converter has locked out it can only be restarted by the removal of the input voltage or by release of the zener diode clamp. Pulse Transformer The pulse transformer that connects the LTC3706 to the LTC3725 performs the dual functions of gate drive duty cycle encoding and gate drive bias supply for the LTC3725 by way of the on-chip full-wave rectifier. The designs of the LTC3725 and LTC3706 have been coordinated so that the transformer turn ratio is: NLTC3725 = 2NLTC3706 where NLTC3725 is the number of turns in the winding connected to the FB/IN+ and FS/IN- pins of the LTC3725 and NLTC3706 is the number of turns in the winding connected to the PT+ and PT- pins of the LTC3706. The winding connected to the LTC3706 must be able to withstand volt-seconds equal to: (V - s)MAX = VCC 2f where VCC is the maximum supply voltage for the LTC3706 and f is the operating frequency of the LTC3706.
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LTC3725
APPLICATIO S I FOR ATIO
Auxiliary Supply
When used with the LTC3706, the LTC3725 does not require an auxiliary supply to provide primary-side gatedrive bias current. After start-up, primary-side gate drive current is provided by the LTC3706 through a small pulse transformer and the LTC3725's on-chip rectifier. However, when used as a standalone primary-side controller, the LTC3725 may require a conventional gate-drive bias supply as shown in Figure 3. The bias supply must be designed to keep the voltage on the VCC pin between the absolute maximum of 15V and the gate-drive undervoltage lockout of 7V. The auxiliary supply is connected in parallel with VCC. The linear regulator maintains VCC at 8V. If the auxiliary supply produces more than 8V, it turns off the external NMOS before the LTC3725 can time out the linear regulator. If the auxiliary supply produces less than 8V, the linear regulator times out and then the voltage on the VCC pin declines to the voltage produced by the auxiliary supply. Slave Mode Operation When the LTC3725 is paired with the LTC3706, multiple pairs can be used to form a PolyPhase converter. In PolyPhase operation, one LTC3725 becomes the "master" while the remainder become "slaves." The master controls start-up in the same manner as for the single-phase converter, while the slaves do not begin switching until receiving PWM information through their own pulse transVIN
NDRV LTC3725 VCC 2.2F GND BAS21 1mH
Figure. 3. Auxiliary Supply for Primary-Side Control
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former from their corresponding LTC3706. To synchronize operation, the SSFLT and VCC pins of the master are connected to the corresponding pins of all the slaves. The master is designated by connection of the frequency set resistor to the FS/IN- pin while this resistor is omitted from the slaves. For the slaves the NDRV pin is connected to the VCC pin. See the following section on PolyPhase Applications for more detail. PolyPhase Applications Figure 4 shows the basic connections for using the LTC3725 and LTC3706 in PolyPhase applications. One of the phases is always identified as the "master," while all other phases are "slaves." For the LTC3725 (primary side), the master performs the open-loop start-up and supplies the initial VCC voltage for the master and all slaves. The LTC3725 slaves are put into that mode by omitting the resistor on FS/IN-. The LTC3725 slaves simply stand by and wait for PWM signals from their respective pulse transformers. Since the SSFLT pins of master and slave LTC3725s are interconnected, a FAULT (overcurrent, etc.) on any one of the phases will perform a shutdown/restart on all phases together. For the LTC3706, the master performs soft-start and voltage-loop regulation by driving all slaves to the same current as the master using the ITH pins. Faults and shutdowns are communicated via the interconnection of the RUN/SS pins. The LTC3706 is put into slave mode by tying the FB pin to VCC.
POWER TRANSFORMER PRIMARY WINDING NP BAS21 AUXILIARY WINDING NA SECONDARY WINDING NS
3725 F03
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3725f
LTC3725
APPLICATIO S I FOR ATIO
VIN+
UVLO VCC
SS/FLT LTC3725 (MASTER) VIN-
SS/FLT FB/IN+ VCC UVLO FS/IN-
LTC3725 (SLAVE)
Figure 4. Connections for PolyPhase
Standalone Primary-Side Operation The LTC3725 can be used to implement a standalone forward converter using optoisolator feedback and a secondary-side voltage reference. Alternately the LTC3725 can be used to implement an open-loop forward converter using the VSLMT pin to regulate against changes in VIN. In either case, the LTC3725 oscillator determines the frequency as found from:
21 * 109 fOSC = RFS(P) + 4200
Note that polyphase operation is not possible in the standalone configuration.
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VOUT+ VBIAS VIN NDRV VCC NDRV FB/IN+ FS/IN- FS/SYNC PT + FB ITH PT - RUN/SS LTC3706 (MASTER)
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*
*
VIN NDRV VCC NDRV RUN/SS FS/SYNC
*
*
PT + PT -
FB ITH PHASE LTC3706 (SLAVE)
3725 F04
Grounding Considerations The LT3725 is typically used in high current converter designs that involve substantial switching transients. Figure 5 illustrates these currents. The switch driver on the IC is designed to drive a large capacitance and, as such, generate significant transient currents. Careful consideration must be made regarding input and local power supply bypassing to avoid corrupting the ground references used by the UVLO and frequency set circuitry. Typically, high current paths and transients from the input supply and any local drive supplies must be kept isolated from GND. By virtue of the topologies used in LT3725 applications, the large currents from the primary switch, as well as the switch drive transients, pass through the sense resistor to ground. This defines the ground connection of the sense resistor as the reference point for both GND and PGND.
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LTC3725
APPLICATIO S I FOR ATIO
Effective grounding can be achieved by considering the return current paths from the sense resistor to each respective bypass capacitor. Don't be tempted to run small traces to separate the grounds. A power ground plane is important as always in high power converters, but care
VIN LTC3725 UVLO VCC FS/IN- GATE GND PGND
SIGNAL GROUND PLANE
Figure 5. High Current Transient Return Paths
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must be taken to keep high current paths away from the GND reference. An effective approach is to use a 2-layer ground plane, reserving an entire layer for GND and an entire layer for PGND. The UVLO and frequency set resistors can then be directly connected to the GND plane.
VCC VIN POWER GROUND PLANE
3725 F05
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3725f
L1 0.33H T1 23.4 x 20.1 x 9.4mm PLANAR 2
VIN
+
*
11 L2 0.85H VOUT+ 3.3V 30A
* 10
36V TO 72V 4 3
1F 100V
1F 100V x2
VIN-
*
9 2.2nF 50V 5.1 1/2W 0.0012 1W 10F 2.2F FCX491A VOUT- 100 HAT2165 x2 HAT2165 x2 1.2 1/4W 220F 6.3V 5.1 1/2W 100F 6.3V x2
*7
B0540W
2.2nF 50V
5 Si7450DP 2.2nF 200V
+
100 0.030 1W 100 68pF 5.1k GATE IS FB/IN+ 1 T2 PT+ LTC3706 8 6 162k 2.2nF 250V 33nF 100k PT- GND PGND RUN/SS SLP REGSD FS/SYNC PHASE ITH 5 470pF 100 SSFLT FS/IN- VSLMT PGND GND FG SW NDRV VCC 0.1F IS- IS+ SG VIN NDRV VCC MODE 3 4 1F
TYPICAL APPLICATIO S
FDC2512
365k
2.74k
* *
UVLO LTC3725
FB
15k
1F
604 470pF 3.3k 47nF
3725 F06a
470pF
33nF
VOUT-
1F, 100V TDK C3225X7R2A105M (1210) 100F, 6.3V TDK C3225X5R0J107M (1210) 220F, 6.3V SANYO 6TPE220M 2.2nF, 250V AC MURATA GA343QR7GD222KW01L (1210) L1: COILCRAFT DO1813P-331HC L2: PULSE PA1294.910 T1: PULSE PA0815 6:6:2:1 T2: PULSE PA0297 2(1.4mH):1:1
Efficiency
94
92 36V
48V 72V
90
EFFICIENCY (%)
88
86
84
5
10
25
30
3725 F06b
20 15 LOAD CURRENT (A)
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LTC3725
100k
680pF
17
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Figure 6. 36V-72V to 3.3V/30A Isolated Forward Converter Using LTC3706
LTC3725
TYPICAL APPLICATIO S
VIN+ 12V VIN- 10F 25V 10F 25V 10F 25V T1 EFD25 1 2 3 MURHB860CT VOUT+ 100pF 1kV 110 0.5W L2 100H L3 100H L1 1.5mH
MMBD914 MMBD914 115k 1 15k 1F 470pF 2 8
1k 3 7 NDRV GATE VCC UVLO LTC3725
SSFLT FS/IN- VSLMT PGND GND 9 6 11 105k
33nF
10F, 25V TDK C3225X7R1E106M (1210) 27F, 100V SANYO MV-AX 1.5F, 63V FILM WIMA MKS2 2.2nF, 250V AC MURATA GA343QR7GD222KW01L L1: PULSE PE-53911 L2, L3: TDK SLF12575T-101M1R9 T1: PULSE PA0700 3T(16H):11:11
Figure 7. 12VIN to 48V/1.5A Isolated Forward Converter Using Optoisolator
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*
*
12
+
4 5 6 Si7370DP x2 100 0.010 1.5W 1nF 100V
10
+
27F 100V
*9
7
* *
27F 100V 1.5F 63V FILM
48V 1.5A
VOUT- -VS 2.4k 2.4k 0.25W 0.25W
1nF 10 IS 4 FB/IN+ 470pF
1k MOC207 1 6
10nF
45.3k 1k 47nF V+ LT1431 1 8 COLL REF
1k 10nF 100V
5
2 2.2nF 250V AC 9.1V
GND-F GND-S 6 5
2.49k
-VS
3725f
LTC3725
PACKAGE DESCRIPTIO U
MSE Package 10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1663)
BOTTOM VIEW OF EXPOSED PAD OPTION
2.794 0.102 (.110 .004)
0.889 0.127 (.035 .005)
1
2.06 0.102 (.081 .004) 1.83 0.102 (.072 .004)
5.23 (.206) MIN
2.083 0.102 3.20 - 3.45 (.082 .004) (.126 - .136)
10
0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT
3.00 0.102 (.118 .004) (NOTE 3) 10 9 8 7 6
0.497 0.076 (.0196 .003) REF
4.90 0.152 (.193 .006) 0.254 (.010)
GAUGE PLANE DETAIL "A" 0 - 6 TYP
3.00 0.102 (.118 .004) (NOTE 4)
12345 0.53 0.152 (.021 .006)
DETAIL "A"
1.10 (.043) MAX
0.86 (.034) REF
0.18 (.007)
SEATING PLANE
0.17 - 0.27 (.007 - .011) TYP
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.50 (.0197) BSC
0.127 0.076 (.005 .003)
MSOP (MSE) 0603
3725f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC3725
RELATED PARTS
PART NUMBER LTC1693 LTC1698 LT1950 LTC3705 LTC3706 LT3710 LTC3726 LT3781 LT3804 LTC3901 DESCRIPTION High Speed Single/Dual N-Channel MOSFET Drivers Secondary Synchronous Rectifier Controller Single Switch Controller 2-Switch Forward Controller and Gate Driver Polyphase Secondary-Side Synchronous Forward Controller Secondary-Side Synchronous Post Regulator Secondary-Side Synchronous Forward Controller "Bootstrap" Start Dual Transistor Synchronous Forward Controller Secondary Side Dual Output Controller with Opto Driver Secondary-Side Synchronous Driver for Push-Pull and Full-Bridge Converter COMMENTS CMOS Compatible Input, VCC Range: 4.5V to 12V Use with the LT1681, Optocoupler Driver, Pulse Transformer Synchronization Used for 20W to 500W Forward Converters 2-Switch Version of LTC3725 Fast Transient Response, Self-Starting Architecture, Current Mode Control For Regulated Auxiliary Output in Isolated DC/DC Converters Similar to the LTC3706 72V Operation, Synchronous Switch Output Regulates Two Secondary Outputs, Optocoupler Feedback Driver and Second Output Synchronous Driver Controller Similar Function to LTC3900, Used in Full-Bridge and Push-Pull Converter
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
LT 1105 * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2005

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